|
★
|
| Compliant with USB specification ver 2.0 |
| - 4 downstream ports |
| - Upstream port supports both high-speed (HS) and full-speed (FS) traffic |
| - Downstream ports support HS, FS, and low-speed (LS) traffic |
| - 1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload) |
| - Backward compatible with USB specification ver 1.1 |
|
| ★ |
| On-chip 8-bit RISC micro-processor |
| - USB optimized operation |
| - Support customized PID, VID by external EEPROM |
|
| ★ |
| Single Transaction Translator (TT) architecture |
| - Cost effective solution for TT through sharing the same TT control logic for all downstream port devices. |
|
| ★ |
Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0 |
| ★ |
Support both individual and gang modes of power management and over- current detection for downstream ports |
| ★ |
Support both bus-power and self-power modes in suspend mode |
| ★ |
Automatic switching between self-powered and bus-powered modes |
| ★ |
Integrated USB2.0 transceiver |
| ★ |
0.35um CMOS technology |
| ★ |
PLL embedded with external 12 MHz crystal |
| ★ |
Operates on 3.3 Volts |
| ★ |
Low power consumption |
| ★ |
Improved output drivers with slew-rate control for EMI reduction |
| ★ |
Internal power-fail detection for ESD recovery |
| ★ |
64-pin LQFP package |
